Ceiling Emitter Ionizer Effectiveness in Electrostatically Controlled Semiconductor Manufacturing
Christian Ceciliano Futscher (1), Bunthay Hong (2), Gregory Larson (3), Larry Levit (4)
(1) Intel Corporation, 1600 Rio Rancho Blvd SE Rio Rancho, NM 87124 USA Tel 505 893 9428, email: christian.ceciliano.futscher@intel.com,
(2) Intel Corporation, 1600 Rio Rancho Blvd SE Rio Rancho, NM 87124 USA Tel 505 991 7296, email: bunthay.hong@intel.com,
(3) Intel Corporation, 2111 NE 25th Ave Hillsboro OR 97124 USA Tel 971 226 7867, email: gregory.larson@Intel.com,
(4) LBL Scientific, 1865 Monte Sereno Dr Alamo CA 94507 USA Tel 925 788 2969, email Doctor.Sparks@gmail.com
Abstract –Electrostatic attraction (ESA) control of micro contamination in cleanroom environments involves avoiding insulators, replacing them with dissipative materials, grounding of conductors and for those items that cannot be so changed, ionization is required. The guideline does not address the importance of ionization for micro contamination control without insulators or ungrounded conductors. Some front end fabs have achieved this. This motivated, a study to learn the effect of global ceiling ionization which showed that in an electrostatically controlled Fab, ceiling emitters did not improve contamination control.
(1) Intel Corporation, 1600 Rio Rancho Blvd SE Rio Rancho, NM 87124 USA Tel 505 893 9428, email: christian.ceciliano.futscher@intel.com,
(2) Intel Corporation, 1600 Rio Rancho Blvd SE Rio Rancho, NM 87124 USA Tel 505 991 7296, email: bunthay.hong@intel.com,
(3) Intel Corporation, 2111 NE 25th Ave Hillsboro OR 97124 USA Tel 971 226 7867, email: gregory.larson@Intel.com,
(4) LBL Scientific, 1865 Monte Sereno Dr Alamo CA 94507 USA Tel 925 788 2969, email Doctor.Sparks@gmail.com
Abstract –Electrostatic attraction (ESA) control of micro contamination in cleanroom environments involves avoiding insulators, replacing them with dissipative materials, grounding of conductors and for those items that cannot be so changed, ionization is required. The guideline does not address the importance of ionization for micro contamination control without insulators or ungrounded conductors. Some front end fabs have achieved this. This motivated, a study to learn the effect of global ceiling ionization which showed that in an electrostatically controlled Fab, ceiling emitters did not improve contamination control.
I. Introduction
Semiconductor Fabs have always used global ceiling emitter ionization. Some bays do not have ionization and do not exhibit obviously higher levels of micro contamination. This, coupled with the high cost of maintenance of the ionization system (both manpower expense and Tool availability loss) has led to this series of tests in a fab with cleanliness level ISO 14644-1 Class 3 or better. The intention was to determine whether a rigorously implemented comprehensive static control program requires the use of blanket ionization coverage from ceiling emitters. It included global ionization which could be switched off for tests. Only micro contamination was studied, not EMI or potential for reticle damage. The object was to subject the wafers in the enclosure to a statistically significant test of particles per wafer pass. The mechanism for contamination on the wafers within the sealed enclosure would be electrostatic movement from the walls of the enclosure to the wafers. II. Field-Driven Micro Contamination
Particles are moved by electric forces, either Coulomb or dielectrophoretic forces [1], [2], [3].[4]. The study was done in a 300 mm fab so FOUPs were used. FOUPs are a specialized plastic |
carrier designed to hold silicon wafers securely and safely in a controlled environment, and to allow the wafers to be transferred
Figure 1. Grounded AMHS adjacent to a dissipative window.
between process tools for processing or measurement [5] The atmosphere within the FOUP in isolated from that of the surrounding environment. If such an absolutely sealed wafer enclosure [in this case, a a FOUP (front opening unified
|
pod)experiences an electric field, particles will be displaced to equilibrium positions within the enclosure and remain stationery. Equilibrium is not a micro contamination event. If the enclosure moves past a charged object, the contents of the enclosure experiences transient fields causing the enclosed particles to move about and is indeed a micro contamination event. Such fields come from charged insulators and ungrounded conductors including personnel if personnel grounding is not well executed. Extensive auditing was done to confirm that indeed there were no insulators or ungrounded conductors outside of the process chambers as prescribed in ANSI/ESD S20.20-2021 [6]. Since the study was of the environment external to the processes, the absence of un ionized insulators in the fab bays was critical to this study.
A. Design of Experiment (DOE) The test was done using a method similar to Welker [7] but in an environment two orders of magnitude cleaner and using state-of-the-art wafer scanning as compared to the sensitivity (100 nm) Tencor 6420 used in the referred article. Data are presented for particles ≥39 nm., measured in a state-of-the-art KLA-Tencor Surfscan SP5. All measurements were made in an environment maintained by the ionization manufacturer. This test was performed 6 weeks after a complete whole bay ionizer maintenance. The philosophy was that rather than measuring ESDA specified parameters of “Discharge Time” and “Voltage Offset”, this study measured the effect the ceiling ionization had on micro contamination. The test must subject the wafers to conditions matching those in real wafer processing. For that reason, the movement of wafers in the most at-risk standard way employed. The Automated Material Handling System (AMHS) is an enclosed grounded metal structure (Figure 1) which serves as a Faraday Shield. Thus, moving the wafers in a FOUP on a manual conveyance called a PGV (personal guided vehicle) was deemed to be a more stringent test and therefore was selected. The way to achieve statistical significance was by increasing the number of samples. This could be done by increasing the number of wafers or the time of exposure. Both were statistically identical. |
Vertical Divider
What was finally selected was a combination of multiple wafers per FOUP, exaggerated transit time in the PGV and multiple FOUPs.
The procedure accepted was to move the FOUP on a PGV through the Fab for an extended period with wafers placed near the top, middle and bottom of the FOUP. Immediately before and right after the extended exposure, the wafers were scanned for particles with a high-resolution scanning Tool and analysis was done on wafer maps generated by the Tool. B. Details of DOE Virgin (un-patterned) wafers were used in a cleaned FOUP. The study employed a state-of-the-art KLA-Tencor Surfscan SP-5 tool to allow the lowest particle size threshold, (18 nm). The exposure was of 4 wafers in one FOUP and 6 wafers in a second FOUP. The exposure consisted of walking the PGV up and down a bay for one hour first under ceiling ionization (ON) and then again with ceiling ionization (OFF). Particle scans were done at the onset of the test (PRE), then after the first walk (POST_I) and after the second walk (POST_NI). This test was done in two different bays. Figure 2. A typical wafer map.
The exposure was for one hour whereas, the normal transit time from tool to tool is typically <5 min. This means particle additions in this test were at least 12x greater than in normal fab operation. .The final PWP numbers were therefore reduced by a factor of 12 which gave representative data and had no effect on the efficacy of the test. |
Figure 3 is a composite of the three scans for one of the wafers. Time moves left to right as the order of the three scans. Differences are particles added (or removed).
After all wafer map readings, the results were tabulated. Figure 3. Compare three wafer maps.
C. Presentation of Data
The wafer maps for 4 wafers were tabulated and the results are shown in Table 1. This represents adders less subtractors for each walk. It is important to keep in mind that the data presented is a tabulation of full hour walks. Table 1. Net particles for each of two walks (Under ceiling ionization environment)
These values are not representative of actual particles added since the exposure time was intentionally so exaggerated. As discussed above, the data are 1200% of normal but representative times are 12x smaller. Those values are shown in Table 2.
Table 2. Net particles added per 5 minutes (Under a ceiling ionization environment) |
Thus, the number of particles >18 nm added with ionization on was 0.2±0.1 and with ionization off it was 0.2±0.01. These two numbers are statistically indistinguishable, indication that ionization did not improve micro-contamination.
III. Conclusions
This study focused on particle micro contamination in mini-environment style fabs with global ceiling ionization. It focused on micro contamination generated within a sealed enclosure (FOUP). The FOUPs in this fab were cleaned regularly in an ionized FOUP washer so the number of particles on the inner walls of the FOUP was very near zero. Thus, ionization external to the FOUP does not have a viable mechanism for contaminating the wafers. The data shows that by eliminating all stationery sources of electric fields (insulators and ungrounded conductors) in the bay, no micro contamination improvement is seen on the wafers within the FOUP (or SMIF). The study also demonstrated that with global ceiling ionization on or off there were no significant differences with particle micro-contamination levels. It is important to add that this study was done in an exceptionally electrostatically neutral environment. Previous studies [8] have shown that when there are insulators in the fab, particles can move about in the FOUP due to Coulomb forces. This study contradicts the previous one because a conspicuous effort was made for the more recent study at removing ALL insulators and grounding ALL conductors. This study does not deal with open cassette fabs or with micro contamination within the process tools themselves. It is also the case that electrostatic damage to reticles within the photo bay was not studied and would likely be a candidate for global ionization. |
IV. References
[1] Stewart Hoenig, Particles on Surfaces Detection, Adhesion, and Removal, Springer US, K.L. Mittal, editor, December 6, 2012
[2] L.B. Levit et al., Contamination Control in Semiconductor Manufacturing, Proc. of SEMICON Taiwan, Taipei, Taiwan, Sept. 1999
[3] Robert P. Donovan, D. S. Ensor, A. C. Clayton, T. Yamamoto, Sandia National Laboratories Particle Deposition Velocity Studies in Silicon Technology, Particles in Gases and Liquids 1 (pp.195-204)
[4] Frank Curran, Master of Science Thesis, The Effects of Static Charge on Silicon Wafers in the Semiconductor Industry, Nov. 1997, The Engineering council of England.
[5] Global PIC Maintenance Task Force, SEMI Aux018 0710 FOUP Load Port Interoperability Report, July 2010.
[6]. EOS/ESD Association, Inc., Rome NY, ANSI/ESD S20.20-2021, Jan.6, 2022
[7] Welker, Roger W., “Equivalence Between Surface Contamination Rates and Class 100 Conditions,” in Proceedings for Institute of Environmental Sciences, 1988.
[8] Long, C.W. Peterman, J., Levit L., 2007 Effects of Ionization on Airborne Particles in a Semiconductor Front-End Fab, Taiwan Electrostatic Discharge Conference November 2007, Hsinchu, Taiwan,
[1] Stewart Hoenig, Particles on Surfaces Detection, Adhesion, and Removal, Springer US, K.L. Mittal, editor, December 6, 2012
[2] L.B. Levit et al., Contamination Control in Semiconductor Manufacturing, Proc. of SEMICON Taiwan, Taipei, Taiwan, Sept. 1999
[3] Robert P. Donovan, D. S. Ensor, A. C. Clayton, T. Yamamoto, Sandia National Laboratories Particle Deposition Velocity Studies in Silicon Technology, Particles in Gases and Liquids 1 (pp.195-204)
[4] Frank Curran, Master of Science Thesis, The Effects of Static Charge on Silicon Wafers in the Semiconductor Industry, Nov. 1997, The Engineering council of England.
[5] Global PIC Maintenance Task Force, SEMI Aux018 0710 FOUP Load Port Interoperability Report, July 2010.
[6]. EOS/ESD Association, Inc., Rome NY, ANSI/ESD S20.20-2021, Jan.6, 2022
[7] Welker, Roger W., “Equivalence Between Surface Contamination Rates and Class 100 Conditions,” in Proceedings for Institute of Environmental Sciences, 1988.
[8] Long, C.W. Peterman, J., Levit L., 2007 Effects of Ionization on Airborne Particles in a Semiconductor Front-End Fab, Taiwan Electrostatic Discharge Conference November 2007, Hsinchu, Taiwan,